Semiconductor devices having a layer of semiconductor material disposed on an insulating substrate are generally known in the art. An example of such a device is a silicon-on-insulator (SOI) semiconductor device which includes a silicon mesa formed on the surface of an insulating material. When the insulating material is a sapphire substrate, the structure is known as a silicon-on-sapphire (SOS) semiconductor device. Metal-oxide-semiconductor (MOS) transistors or other active devices are formed in and on the silicon mesa. MOS/SOI transistors generally have higher speed and improved radiation hardness in comparison with MOS transistors formed in bulk silicon.
MOS/SOI transistors have a higher degree of radiation hardness with respect to transient-type radiations (gamma pulses, x-ray pulses and high-energy single particles) because, when compared to bulk silicon devices, there is a smaller volume of silicon present in which photocurrent generation can occur. However, radiation-induced charge carriers are also generated within the insulating materials, such as the sapphire substrate. Some of the charges generated within the sapphire substrate are injected into the transistor formed in the silicon mesa. These injected charges can be collected at nodes and impose an upper limit to device performance in transient-type radiation environments. Also, radiation-induced positive charges accumulate in the sapphire substrate in the region adjacent the silicon mesa/sapphire interface when exposed to any type of high-energy radiation. The positive charge in the sapphire substrate attracts a corresponding negative charge in the region of the silicon mesa adjacent the interface. This accumulation of negative charges can in certain devices, such as N-channel transistors, create a back-channel or electron flow which is not controlled by the gate electrode.
Numerous solutions have been proposed to reduce back-channel leakage currents. However, most of these solutions are directed to the silicon mesa. For example, P. Vasudev in U.S. Pat. No. 4,509,990, entitled "Solid Phase Epitaxy and Regrowth Process With Controlled Defect Density Profiling For Heteroepitaxial Semiconductor On Insulator Composite Substrates," issued Apr. 9, 1985, discloses the use of a high defect density layer within the silicon mesa. This high defect density layer, which may be a residual damage interface layer or an annealed interface layer, is formed during the ion implantation step used in the solid-phase epitaxy growth process. The high defect density layer is positioned in the silicon mesa adjacent to the silicon/sapphire interface. The high defect density layer reduces the leakage current along the back-channel because the damaged crystal structure reduces the mobility of the charge carriers along this region.
Back-channel leakage currents can also be reduced by selectively doping portions of the silicon mesa. U.S. Pat. No. 4,183,134, entitled "High Yield Processing For Silicon-On-Sapphire CMOS Integrated Circuits," issued Jan. 15, 1980 to H. Oehler et al. is an example of such a process. In N-channel devices, P-type materials are ion implanted into the channel region adjacent the silicon/sapphire interface. This region near the silicon/sapphire interface has a heavier P-type doping concentration so as to increase the amount of radiation-induced positive charge within the sapphire substrate needed before the back-channel in the silicon mesa is turned on.
Since the back-channel leakage problem is attributed to charge carrier generation and trapping within the insulating substrate, it would be desirable to process the substrate in a manner to reduce the effect of these charge carriers on the silicon transistor. This would then allow for normal processing techniques to be used to form the semiconductor device within the silicon mesa, rather than using the processing techniques which employ a heavily doped region in the portion of the channel adjacent the silicon/sapphire interface or a defect region within the silicon layer.